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| power management & multimarket data sheet v1.1, 2013-08-14 final 2nd generation fl controller for fluorescent lamp ballasts ICB2FL03G
edition 2013-08-14 published by infineon technologies ag 81726 munich, germany ? 2013 infineon technologies ag all rights reserved. legal disclaimer the information given in this docu ment shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infineo n technologies hereby disclaims any and all warranties and liabilities of any kind, including wit hout limitation, warranties of non-infringement of in tellectual property rights of any third party. information for further information on technology , delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contai n dangerous substances. for information on the types in question, please contact the neares t infineon technologies office. infineon technologies components may be used in life-s upport devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safe ty or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. ICB2FL03G controller for fluorescent lamp ballasts final data sheet 3 v1.1, 2013-08-14 trademarks of infineon technologies ag aurix?, c166?, canpak?, ci pos?, cipurse?, econopac k?, coolmos?, coolset?, corecontrol?, crossav e?, dave?, di-pol?, easypim?, econobridge?, econodual?, econopim?, econopack?, eicedriver?, eupec?, fcos?, hitfet?, hybridpack?, i2rf?, isoface?, isopack?, mipaq?, modstack?, my-d?, novalithic?, optimos?, origa?, powercode?; primarion?, pr imepack?, primestack?, pr o-sil?, profet?, rasic?, reversave?, satric?, si eget?, sindrion?, sipmos?, smartl ewis?, solid flash?, tempfet?, thinq!?, trenchstop?, tricore?. other trademarks advance design system? (ads) of agilent te chnologies, amba?, arm?, multi-ice?, keil?, primecell?, realview?, thumb?, vision? of arm limited, uk. autosar? is licensed by autosar development partnership. bluetooth? of bluetooth sig inc. cat-iq? of dect forum. colossus?, firstgps? of trimble navigation ltd. emv? of emvc o, llc (visa holdings in c.). epcos? of epcos ag. flexgo? of microsoft corp oration. flexray? is licensed by flexray consortium. hyperterminal? of hilgraeve incorporated. iec? of commission electrot echnique internationale. irda? of infrared data association corporation. iso? of international organization for standardization. matlab? of mathworks, inc. maxim? of maxim integrated products, inc. microtec?, nucleus? of mentor graphics corporation. mipi? of mipi allianc e, inc. mips? of mips technologies, inc., u sa. murata? of murata manufacturing co., microwave office? (mwo) of applied wave research inc., omnivision? of omnivision technologies, inc. openwave? openwave systems inc. red hat? red hat, inc. rfmd? rf micro devices, inc. sirius? of si rius satellite radio inc. solaris? of sun microsystems, inc. spansion? of spansion llc ltd. symbian? of symbian software limited. taiyo yuden? of taiyo yuden co. teaklite? of ceva, inc. tektro nix? of tektronix inc. toko? of toko kabushiki kaisha ta. unix? of x/open company limited. verilo g?, palladium? of cadence design systems, inc. vlynq? of texas instruments incorpor ated. vxworks?, wind river? of wind ri ver systems, inc. zetex? of diodes zetex limited. last trademarks update 2011-11-11 revision history page or item subjects (major changes since previous revision) final v1.1, 2013-08-14 page 54-55 inserted chapter 5.3.4 parameter limits for extended temperature range down to -40c final v1.0 2013-02-14 page 45 changed max value for i hsvccqu1 from 270a to 280a changed min value for v hsvccon from 9.9v to 9.8v page 48 changed min value for v pfcgdrise from 105ns to 100ns typo correction: v pfcgdrise & v pfcgdfall --> t pfcgdrise & t pfcgdfall page 50 changed min value for t lsgdrise from 105ns to 100ns page 52 changed min value for t hsgdrise from 140ns to 120ns typo correction: t hsgdrise & t hsgdfall --> t hsgdrise & t hsgdfall ICB2FL03G controller for fluorescent lamp ballasts table of contents final data sheet 4 v1.1, 2013-08-14 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2nd generation fl-controller for fluorescent lamp ballasts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1 pin configuration and functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2 pg-dso-16 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3 pin functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1 typical application circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2 normal startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.1 operating levels from uvlo to soft start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2.2 operating levels from soft start to run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3 filament detection during start-up and run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.1 start-up with broken low side filament . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.2 low side filament detection during run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.3 start-up with broken high side filament . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.4 pfc preconverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.4.1 discontinuous conduction an d critical conduction mode operation . . . . . . . . . . . . . . . . . . . . . . . 23 2.4.2 pfc bus voltage sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.4.2.1 bus overvoltage and pfc open loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.4.2.2 bus voltage 95 % and 75 % sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.4.3 pfc structure of mixed signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.4.4 thd correction via zcd signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.5 detection of end-of-life and rectifier effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.5.1 detection of end of life 1 (eol1) ? lamp overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.5.2 detection of end of life 2 (eol2) ? rectifier effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.6 detection of capacitive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.6.1 capacitive load 1 (idling detection ? current mode preh eating) . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.6.2 capacitive load 2 (overcur rent / operation below resonance) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.6.3 adjustable self-adapting dead time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.7 emergency lighting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.7.1 short-term pfc bus undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.7.2 long-term pfc bus undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.8 built-in customer test mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.8.1 preheating test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.8.1.1 skip the preheating phase ? set rtph pin to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.8.1.2 ic remains in preheating phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.8.2 deactivation of the filament detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.8.3 built-in customer test mode (clock acceleration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.8.3.1 enabling of the clock acceleration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.8.3.2 starting the chip with accelerated clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.1 features during different operating mode s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.2 operating flow of the start-up procedure into run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.3 auto restart and latched fault condition mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table of contents ICB2FL03G controller for fluorescent lamp ballasts table of contents final data sheet 5 v1.1, 2013-08-14 4 protection functions matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.3 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.3.1 power supply section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.3.2 pfc section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.3.2.1 pfc current sense (pfccs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.3.2.2 pfc zero current detection (pfczcd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.3.2.3 pfc bus voltage sense (pfcvs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.3.2.4 pfc pwm generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.3.2.5 pfc gate drive (pfcgd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.3.3 inverter section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.3.3.1 low side current sense (lscs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.3.3.2 low side gate drive (lsgd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.3.3.3 inverter control run (rfrun) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.3.3.4 inverter control preheating (rfph, rtph) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.3.3.5 restart after lamp removal (res) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.3.3.6 lamp voltage sense (lvs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.3.3.7 high side gate drive (hsgd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.3.3.8 timer section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.3.3.9 built-in customer test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.3.4 parameter limits for extended temperature range down to -40c . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6 application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.1 schematic ballast 54w t5 single lamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.2 bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.3 multi lamp ballast topologies (series co nnection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 7 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 7.1 outline dimensions of pg-dso-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 ICB2FL03G controller for fluorescent lamp ballasts list of figures final data sheet 6 v1.1, 2013-08-14 figure 1 typical application circuit of ballast for a single fluor escent lamp . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2 pg-dso-16 package (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3 application circuit of ballast for a single fluorescent lamp (fl). . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 4 typical startup procedure in run mode (in normal oper ation) . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 5 typical startup procedure in run mode (in normal oper ation) . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 6 typical variation of operating frequency during startup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 figure 7 lamp voltage versus frequency during the different st artup phases . . . . . . . . . . . . . . . . . . . . . . 18 figure 8 start-up with open low side filament. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 9 restart from open low side filament . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 10 open low side filament run mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 11 restart from open ls filament . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 12 start-up with open high side filament . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 13 restart from open high side filament. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 14 operating frequency and on time versus power in dcm and critcm operation . . . . . . . . . . . . 23 figure 15 pfc bus voltage operating level and error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 figure 16 structure of the mixed digital and analog control of the pfc preconverter . . . . . . . . . . . . . . . . . 25 figure 17 thd optimization using adjustable pulse width extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 18 end of life and rectifier effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 19 end of life (eol1) detection, lamp voltage versus ac lvs current . . . . . . . . . . . . . . . . . . . . . . 27 figure 20 end of life (eol2) detection, lamp voltage versus dc lvs current . . . . . . . . . . . . . . . . . . . . . . 28 figure 21 capacitive and inductive operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 22 capacitive mode 1 operation without load during run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 23 capacitive mode 2 ? operation with overcurrent. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 24 dead time of on and off of the half-bridge drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0 figure 25 bus voltage drop below 75% (rated bus voltage) for t < 800 ms during run mode. . . . . . . . . . 31 figure 26 bus voltage drop below 75% (rated bus voltage) for t > 800 ms during run mode. . . . . . . . . . 32 figure 27 start-up with preheating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 28 start-up without preheating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 29 start-up with preheating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 30 start-up without preheating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 31 deactivation via res pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 32 deactivation via lvs pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 33 clock acceleration (built in customer test mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 34 monitoring features during different operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 35 operating flow during start-up procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 36 operating process during start-up mode and handling of fault conditions . . . . . . . . . . . . . . . . . 39 figure 37 application circuit of ballast for single fluorescent lamp voltage mo de preheating . . . . . . . . . . 56 figure 38 bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 39 application circuit of ballast for two fluorescent lamps voltage mo de preheating . . . . . . . . . . . 58 figure 40 package outline with creepage distance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 list of figures ICB2FL03G controller for fluorescent lamp ballasts list of tables final data sheet 7 v1.1, 2013-08-14 table 1 pin configuration for pg-dso-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 2 specified acceleration factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 3 protection functions matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 list of tables ICB2FL03G controller for fluorescent lamp ballasts final data sheet 8 v1.1, 2013-08-14 2nd generation fl-controller for fluorescent lamp ballasts product highlights ? lowest count of external components ? 650 v half-bridge driver with coreless transformer technology ? supports customer in-circuit te st mode for reduced tester time ? supports multi-lamp designs (series connection) ? integrated digital timers up to 40 seconds ? numerous monitoring an d protection features for highest reliability ? very high accuracy of frequencies and timers over the whole temperature range ? very low standby losses pfc features ? discontinuous mode pfc for load range 0 to 100% ? integrated digital compensation of pfc control loop ? improved compensation for low thd of ac input current, also in dcm operation ? adjustable pfc current limitation lamp ballast inverter features ? adjustable detection of overload and rectifier effect (eol) ? detection of capacitive load operation ? improved ignition control allows operation close to the magnetic saturation of the lamp inductors ? restart with skipped preheating on short interrup tions of line voltage (for emergency lighting) ? parameters adjustable by resistors only ? pb-free lead plat ing; rohs-compliant figure 1 typical application circuit of ballast for a single fluorescent lamp description the fl controller ICB2FL03G is designed to control fluorescent lamp ballast, including a discontinuous mode power factor correction (pfc), lamp inverter control and a high-voltage level shift half-bridge driver. the control concept covers requirements for t5 lamp ba llasts for single and multi-lamp designs (series connection supported). ICB2FL03G is based on the 2nd-generation fl controller technology, is easy to use and simple to design in. this makes the ICB2FL03G a basis for cost-effective solutions for fluorescent lamp ballasts with high reliability. figure 1 shows a typical application circuit of ballast fo r a single fluorescent t8 lamp with current mode preheating. rfrun rfph rtph vcc pfczcd pfcgd pfcvs pfccs hsgd hsvcc hsgnd lsgd lscs lvs gnd vin ICB2FL03G res ICB2FL03G controller for fluorescent lamp ballasts pin configuration and functionality final data sheet 9 v1.1, 2013-08-14 1 pin configuration and functionality 1.1 pin configuration 1.2 pg-dso-16 package figure 2 pg-dso-16 package (top view) table 1 pin configuration for pg-dso-16 pin symbol function 1 lsgd low side gate drive (inverter) 2 lscs low side current sense (inverter) 3 vcc supply voltage 4 gnd low side ground 5 pfcgd pfc gate drive 6 pfccs pfc current sense 7 pfczcd pfc zero current detector 8 pfcvs pfc voltage sense 9 rfrun set r for run frequency 10 rfph set r for preheat frequency 11 rtph set r for preheating time 12 lvs lamp voltage sense 13 res restart after lamp removal 14 hsgnd high side ground 15 hsvcc high side supply voltage 16 hsgd high side gate drive (inverter) hsvcc hsgnd rfph res lvs pg-dso-16 (150mil) rfrun pfcvs pfczcd ICB2FL03G gnd hsgd lscs pfcgd lsgd pfccs vcc rtph 8 7 4 2 5 1 6 3 9 10 13 15 12 16 11 14 ICB2FL03G controller for fluorescent lamp ballasts pin configuration and functionality final data sheet 10 v1.1, 2013-08-14 1.3 pin functionality lsgd (low-side gate drive, pin 1) the gate of the low-side mosfet in a half-bridge inverter topology is controlled by this pin. there is an active l-level during uvlo (under voltage lockout) and limitat ion of the max h-level at 11.0 v during normal operation. in order to turn on the mosfet softly (with a reduced di drain /dt); the gate voltage typi cally rises within 245 ns from l-level to h-level. the fall time of th e gate voltage is less than 50 ns in order to turn off quickly. this measure produces different switching speeds during turn-on and turn-o ff as it is usually achieved with a diode parallel to a resistor in the gate drive loop. it is reco mmended to use a resistor of typically 10 ? between drive pin and gate in order to avoid oscillati ons and in order to sh ift the power dissipation of discha rging the gate capacitance into this resistor. the dead time between the lsgd signal and hsgd signal is self-adapting between 1.05 s and 2.1 s. lscs (low-side current sense, pin 2) this pin is directly connected to th e shunt resistor which is located between the source terminal of the low-side mosfet of the inverter and ground. internal clamping structures and filtering measures allo w for sensing the source current of the low-side inverter mosfet without additional filter components. the first threshold is 0.8 v. if this threshold is excee ded for longer than 500 ns during preheat or run mode, an inverter overcurrent is detected and causes a latched shut down of the ic. the ignition control is activated if the sensed slope at the lscs pin reaches typically 205 mv/ s 25 mv/ s and exceeds the 0.8 v threshold. this stops the frequency decrease and waits for ignition. the i gnition control is now cont inuously monitored by the lscs pin. the ignition control is des igned to handle choke operation in saturation during ignition in order to reduce the choke size. if the sensed current signal exceeds a second threshold of 1.6 v for longer than 500 ns during start-up, soft start, ignition mode and pre-run, the ic changes over into latched shutdown. there are further thresholds active at this pin during ru n mode that detect capacitive mode operation. an initial threshold at 50 mv needs to sense a positive current during the second 50 % on-time of the low-side mosfet for proper operation (cap. load 1). a second threshold of -5 0mv senses the current before the high-side mosfet is turned on. a voltage level belo w this threshold indicates faulty operation (cap. load 2). finally a third threshold at 2.0 v senses even short overcurrent during turn-on of t he high-side mosfet, typical fo r reverse recovery currents of a diode (cap. load 2). if any of t hese three comparator thresholds indica tes incorrect operating conditions for longer than 620 s (cap. load 2) or 2500 ms (cap. load 1) in run mode, the ic turns off the gates and changes into fault mode due to detected capacitive mo de operation (non-zero voltage switching). the threshold of -50 mv is also used to adjust the dead ti me between turn-off and turn-on of the half-bridge drivers in a range of 1.05 s to 2.1 s during all operating modes. vcc (supply voltage, pin 3) this pin provides the power supply of the ground related section of the ic. there is a turn-on threshold at 14.0 v and an uvlo threshold at 10.6 v. t he upper supply voltage level is 17.5 v. there is an internal zener diode clamping v cc at 16.3 v (at i vcc = 2 ma typically). the maximum zener curr ent is internally limited to 5 ma. an external zener diode is required for higher current leve ls. current consumpt ion during uvlo and during fault mode is less than 170 a. a ceramic capacitor close to the supply and gnd pin is required in order to act as a low- impedance power source for gate drive and logic signal currents. in order to skip preheating after short interruptions to the mains supply it is necessary to feed the start-up current (160 a) from the bus voltage. note: for external v cc supply, see notes in the flowchart ( section 3.3 ). ICB2FL03G controller for fluorescent lamp ballasts pin configuration and functionality final data sheet 11 v1.1, 2013-08-14 gnd (ground, pin 4) this pin is connected to ground and represents the ground level of the ic for supply voltage, gate drive and sense signals. pfcgd (pfc gate drive, pin 5) this pin controls the gate of the mosf et in the pfc preconverter designed in boost topology. there is an active l-level during uvlo and limitation of the max h-level at 11 .0 v during normal operation. in order to turn on the mosfet softly (with a reduced di drain /dt), the gate drive voltage rises within 245 ns from l-level to h-level. the fall time of the gate voltage is less than 50 ns in order to turn off quickly. a resistor of typically 10 ? between the drive pin and gate is recomme nded in order to avoi d oscillations and in order to shift the power dissipation of discharg ing the gate capacitanc e into this resistor. the pfc section of the ic controls a boost converter as a pfc preconverter in discontinuous conduction mode (dcm). control usually starts with gate drive pulses with a fixed on-time of typically 4.0 s at v acin =230v, increasing up to 24 s and with an off-time of 47 s. as soon as sufficient zero current detector (zcd) signals are available, the operation mode changes from fixed frequency operation to operation with variable frequency. the pfc works in critical conduction mode operation (critcm) when rated and / or medium load conditions are present. this means triangular-shaped currents in the boost converter choke without gaps and variable operating frequency. during low loads (detected by an internal co mpensator) operation is in discontinuous conduction mode (dcm) ? i.e., triangular-shaped currents in the boost co nverter choke with gaps when reaching the zero current level and variable operating frequency in orde r to avoid steps in the consumed line current. pfccs (pfc current sense, pin 6) the voltage drop across a shunt resistor located between the source of the pfc mosfet and gnd is sensed with this pin. if the level exceeds a thre shold of 1.0 v for longer than 200 ns, the pfc gate drive is turned off as long as the zero current detector (zcd) enables a new cycle. if no zcd signal is available within 52 s after turn-off of the pfc gate drive, a new cycle is in itiated from an internal start-up timer. pfczcd (pfc zero current detector, pin 7) this pin senses the point of time when the current through boost inductor becomes zero during off-time of the pfc mosfet in order to initiate a new cycle. the moment of interest appears when the voltage of the separate zcd winding changes from the positive to negative level, which represents a voltage of zero at the inductor windings and therefore the end of current flow from the lower input voltage level to the higher output voltage level. there is a th reshold with hysteresis ? for increasing level 1.5 v, for decreasing level 0.5 v ? which detects the change in inductor voltage. a resistor, connected between zcd winding and pin 7, limit s the sink and source current of the sense pin when the voltage of the zcd winding exceeds the internal clampi ng levels (6.3 v and -2.9 v typically @ 5 ma) of the ic. if the sensed voltage level of the zcd winding is not suffi cient (e.g. during start-up), an internal start-up timer will initiate a new cycle every 52 s after turn-off of the pfc gate drive. the so urce current flowing out of this pin during the on-time of the pfc-mosfet indicates the voltage leve l of the ac supply voltag e. during low input voltage levels the on-time of the pfc-mosfet is increased in order to minimize gaps in the line current during zero crossing of the line voltage and improve the thd (total ha rmonic distortion) of the lin e current. optimization of the thd is possible by trimming of the resistor between this pin and the zcd winding. pfcvs (pfc voltage sense, pin 8) the intermediate circuit voltage (bus voltage) at the smoo thing capacitor is sensed by a resistive divider at this pin. the internal reference voltage for rated bus voltage is 2.5 v. there are further th resholds at 0.3125 v (12.5 % of the rated bus voltage) for the detecti on of open control loop, at 1.875 v (75 % of the rated bus voltage) for the detection of undervoltage, and at 2.725 v (109 % of the rated bus voltage) for the detection of overvoltage. the ICB2FL03G controller for fluorescent lamp ballasts pin configuration and functionality final data sheet 12 v1.1, 2013-08-14 overvoltage threshold operates with a hy steresis of 100 mv (4 % of the rate d bus voltage). for the detection of successful start-up, the bus voltage is sensed at 95 % (2.375 v). it is recommended to use a small capacitor between this pin and gnd as a spike suppression filter. in run mode, a pfc overvoltage stops the pfc gate drive within 5 s. as soon as the bus voltage is less than 105 % of the rated level, the gate drives are enabled agai n. if the overvoltage lasts fo r longer than 625 ms, inverter overvoltage is detected and the inverter turns off the gate drives also. this causes powerdown and powerup when v bus <109%. a bus undervoltage (v bus > 75 %) or inverter overvoltage during run mode is handled as a fault u. in this situation the ic changes into powerdown mode and generates a delay of 100 ms by an internal timer. then startup conditions are checked and if valid, a fu rther startup is initiated. if startup conditions are not valid, a further delay of 100 ms is generated. this procedure is repeated a maximum of seven times. if startup is successful withi n these seven cycles, the situation is interpreted as a short inte rruption of the mains supply and the preh eating is skipped. any further startup attempt is initiated to include the preheating. rfrun (set r for run frequency, pin 9) a resistor from this pin to ground sets the operating fr equency of the inverter during run mode. the typical run frequency range is 20 khz to 120 khz. the set resistor r_rfrun can be calculated, based on the run frequency f run according to the equation: rfph (set r for preheat frequency, pin 10) a resistor from this pin to ground, together with the resi stor at pin 9, sets the oper ating frequency of the inverter during preheating mode. the typical preheating frequency range is from the run frequency (as a minimum) to 150 khz. the set resistor r_rfph can be calc ulated, based on the preheating frequency f ph and the resistor r rfrun according to the equation: rtph (set r for preheating time, pin 11) a resistor from this pin to ground sets the preheating ti me of the inverter during preheating mode. a set resistor range from zero to 25 k ? corresponds to a range of preheating time s from zero to 2500 ms subdivided into 127 steps, as expressed below: lvs (lamp voltage sense, pin 12) before startup this pin senses a current fed from the rectified line voltage via resistors through the high-side filaments of the lamp for detection of an inserted lamp. run frun f hz r ? = 8 10 5 1 10 5 8 ? ? ? = hz r f r r rfrun ph rfrun rfph = k ms t r eheating rtph 100 pr ICB2FL03G controller for fluorescent lamp ballasts pin configuration and functionality final data sheet 13 v1.1, 2013-08-14 the sensed current fed into the lvs pin has to exceed 12 a typically at a voltage level of 6.0 v at the lvs pin. the reaction on the high side filament detection is mirrored at the res pin (see pin 13). in addition, the detection of available mains supply after an interruption is sensed by this pin. together with the res pin, the ic can monitor the lamp removal of one lamp path (series connection of la mps is possible). if the func tionality of this pin is not required, it can be disabled by connecting this pin to ground. during run mode the lamp voltage is monitored with this pin by sensing a current proportional to the lamp voltage via resistors. an overload is indicated by an excessiv e lamp voltage. if the peak-t o-peak lamp voltage causes a peak-to-peak current above a threshold of 210 a pp for longer than 620 s, a fault eol1 (end-of-life) is assumed. if the dc current at the lvs pin exceeds a threshold of 42 a for longer than 2500 ms, a fault eol2 (rectifier effect) is assumed. the levels of ac sense current and dc sense current can be set separately by an external rc network. note that in the case of deactivation of the l vs pin, reactivation starts wh en the voltage at the lvs pin exceeds v lvsenable1 in run mode. res (restart, pin 13) a source current flowing out of this pin via resistor and filament to ground monitors the existence of the low-side filament of the fluorescent lamp for restart after lamp removal. a capacitor from this pin directly to ground eliminates a superimposed ac voltage that is generat ed as a voltage drop across the low-side filament. with a second sense resistor, the filament of a parallel lamp can be included in the lamp removal sensing. note that during startup the chip supply voltage v cc has to be below 14.0 v before v res reaches the filament detection level. during typical start-up with connected filaments of the lamp a current source i res3 (-21.3 a) is active as long as v cc > 10.6 v and v res < v res1 (1.6 v). an open low-side filament is detected when v res > v res1 . such a condition will prevent the start-up of the ic. in additi on, the comparator th reshold is set to v res2 (1.3 v) and the current source changes to i res4 (-17.7 a). the system is then waiting for a voltage level lower than v res2 at the res pin to indicate a connected low- side filament, which will enable the start-up of the ic. an open high-side filament is detect ed when there is no sink current i lvssink (< 12 a typ.) into the lvs pin before the v cc start-up threshold is reached. under these cond itions the current source at the res pin is i res1 (-42.6 a) as long as v cc > 10.6 v and v res ICB2FL03G controller for fluorescent lamp ballasts functional description final data sheet 15 v1.1, 2013-08-14 figure 4 typical startup procedure in run mode (in normal operation) followed at the end of the start-up hysteresis (phase 2, figure 4 ) v cc > 14.0 v and before phase 3 is active, a second level of detection activity senses for 130 s (propagation delay of the ic) whether the bus voltage is between 12.5 % and 105 %. if the previous bus voltage co nditions are fulfilled and the filaments are detected, the ic starts the operation with an interna lly fixed startup frequency of typically 135 khz (all gates are active). if the bus voltage reaches a level of 95 % of the rated bu s voltage within 80 ms at the latest (phase 3, figure 4 ), the ic enters the soft start phase. during soft start (phase 4 , figure 4 ), the start-up frequency shifts from 135 khz down to the set preheating frequency ( section 2.2.2 ). in the soft start phase, the lamp voltage rises and the chip supply voltage reaches its working level from 10.6 v < v cc < 17.5 v. after the soft start has finished , the ic enters the preheating mode (phase 5, figure 4 ) for preheating the filaments (adjustable time) in order to extend the life cycle of the fl filaments. on finishing preheating, the controller starts ignition (phase 6, figure 4 ). during the ignition phase, the frequency decreases from the set preheati ng frequency down to the set operation frequency (adjustable, see section 2.2.2 ). if ignition is successful, the ic enters the pre-run mode (phase 7, figure 4 ). this mode is provided in order to prevent a malfunct ion of the ic due to an unstable system ? e.g., the lamp parameters are not in a steady state condition. after finishing the 625 ms pre-run phase, the ic switches over to the run mode (phase 8, figure 4 ) with complete monitoring. mode / time frequency / lamp voltage 42 khz soft start preheating ignition pre-run run mode into normal operation 100 khz 135 khz frequency lamp voltage 0 khz v cc = 17.5 v v cc = 14.0 v v cc = 10.6 v monitoring uvlo chip supply voltage v cc chip supply voltage v cc = 0 v rated bus voltage v bus mode / time mode / time 100 % rated bus voltage start up 1 2 3 5 4 6 7 8 95 % 30 % 60ms 35ms 80ms 11ms 0 - 2500 ms 40 - 237ms 625 ms 50 khz ICB2FL03G controller for fluorescent lamp ballasts functional description final data sheet 16 v1.1, 2013-08-14 2.2.1 operating levels from uvlo to soft start this section describes the operating flow from phase 1 (uvl o) to phase 4 (soft start) in detail. the control of the ballast is able to start the operation within less than 100 ms (ic in active mode). this is achieved by a small start- up capacitor (about 1 f c12 and c13 ? fed by start-up resistors r11 and r12 in figure 3 ) and the low current consumption during the uvlo (i vcc = 130 a ? phase 1, figure 5 ) and start-up hysteresis (i vcc = 160 a ? defines the start-up resistors ? phase 2, figure 5 ) phases. the chip supply stage of th e ic is protected against overvoltage via an internal zener clamping network, which clamps th e voltage at 16.3 v and allows a current of 2.5 ma. for clamping currents above 2.5 ma, an external zener diode (d9, figure 3 ) is required. 1) figure 5 typical startup procedure in run mode (in normal operation) 1) i gate depends on mosfet v cc 16.0 v 14.0 v 10.6 v uvlo soft start i vcc 130 a 1.6 v v res i res -21.3 a i lvs > 18 a < 160 a < 6.0 ma + i gate < 210a pp v bus 95 % 30 % 17.5 v 100 % 1 2 3 4 135 khz 100 khz frequency lamp voltage frequency / lamp voltage monitoring start up ICB2FL03G controller for fluorescent lamp ballasts functional description final data sheet 17 v1.1, 2013-08-14 if v cc exceeds the 10.6 v level and stays below 14.0 v (start-up hyst eresis ? phase 2, figure 5 ), the ic checks whether the lamps are assembled by detec ting a current across the filaments. the low side filaments are checked from a source current of typical i res3 = - 21.3 a flowing out of pin 13 res ( figure 5 i res ). this current produces a voltage drop of v res < 1.6 v (filament is ok) at the low side filament sense resistor (r 36 in figure 3 ), connected to gnd (via low si de filament). an open low side filament is detected (see section 2.3.2 ), when the voltage at the res pin exceeds the v res > 1.6 v threshold ( figure 5 v res ). the high side filaments are checked by a current of i lvs > 12 a typically via resistors r41, r42, r43 and r44 ( figure 3 ) into the lvs pin 12 (for a single lamp operation). an unused lvs pin has to be disabled via connection to gnd. an open high side filament is detected (see section 2.3.3 ) when there is no sink current into the lvs pin. this causes a higher source current out of the res pin (typically 42.6 a / 35.4 a) in order to exceed v res > 1.6 v. in the case of defective filaments, the ic keeps monitoring until an adequate current from the res or the lvs pin is present (e.g. in case of removal of a defective lamp). when v cc exceeds the 14.0 v threshold ? by the end of the start-up hysteresis in phase 2 , figure 5 ? the ic waits for 130 s and senses the bus voltage. if the rated bus voltage is in the corridor of 12.5 % < v busrated < 105 %, the ic powers up the system and enters phase 3 ( figure 5 v busrated > 95 % sensing); if not, the ic initiates a uvlo until the chip supply voltage falls below v cc < 10.6 v. as soon as the condition for a power-up is fulfilled, the ic starts the inverter gate operation with an internal fixe d start-up frequency of 135 k hz. the pfc gate drive starts with a delay of approx. 300 s. next, the bus voltage will be checked for a rated level above 95 % for a duration of 80 ms (phase 3, figure 5 ). when leaving phase 3, the ic enters the soft start phase and shifts the frequency from the internal fixed start-up frequency of 13 5 khz down to the set preheating frequency ? e.g. f rfph = 100 khz. 2.2.2 operating levels from soft start to run mode this section describes the operating flow from phase 5 (pre heating mode) to phase 8 (run mode) in detail. in order to extend the lifetime of the filame nts, the controller enters ? after the soft start phase ? the preheating mode (phase 5, figure 6 ). the preheating frequency is set by resistors r22 pin r fph to gnd in combination with r21 ( figure 3 ) typ. 100 khz e.g. r22 = 8.2 k ? in parallel to r21 = 11.0 k ? (see figure 3 , rfrun pin). the preheating time can be selected by the programming resistor (r23 in figure 3 ) at pin rtph from 0 ms up to 2500 ms (phase 5, figure 6 ). figure 6 typical variation of operating frequency during startup 65khz 50khz 40khz preheating ignition normal operation run 135khz softstart frequency f , v lamp voltage 40-237ms t 10ms 0-2500ms pre-run 625 ms softstart proceeds in 15 steps 650s according f ph = (135khz - f ph )/ 15steps. ignition proceeds in 127 steps 324s according f ign = (f ph -f run )/ 127steps. preheating frequency with 8.7 k ? resistor from pin rfph to gnd run frequency with a 12.0 k ? resistor from pin rfrun to gnd start-up 0.8 v v lscs 3 5 4 6 7 8 ICB2FL03G controller for fluorescent lamp ballasts functional description final data sheet 18 v1.1, 2013-08-14 during ignition (phase 6, figure 6 ), the operating frequency of the inverter is shifted downward in t typ =40ms (t max = 237 ms) to the run frequency set by a resistor (r21 in figure 3 ) at pin rfrun to gnd (typically 45 khz with an 11.0 k ? resistor). during this frequen cy shifting, the voltage and curr ent in the resonant circuit will rise when the operation is close to the re sonant frequency with increasing voltage across the lamp. the ignition control is activated if the sensed slope at the lscs pin reaches typically 205 mv/ s 25 mv/ s and exceeds the 0.8 v threshold. this stops the decrease of the frequency and waits for ignition. the ignition control is now continuously monitored by the lscs pin. the maximum duration of the ignition procedure is limited to 237 ms. if there is no ignition within this time frame, the ignition control is di sabled and the ic changes over into the latched fault mode. furthermore, in order to reduce the size of the lamp chok e, the ignition control is designed to operate with a lamp choke in magnetic saturation during ignition. for operatio n in magnetic saturation during ignition; the voltage at the shunt at the lscs pin 2 has to be v lscs = 0.75 v when the ignition voltage is reached. if ignition is successful, the ic enters the pre-run mode (phase 7, figure 6 ). the pre-run mode is a safety mode in order to prevent a malfunction of the ic due to an unstable system ? e.g., the lamp parameters are not in a steady state condition. after 625 ms pre-run mode, the ic changes to the run mode (phase 8, figure 6 ). the run mode monitors the complete system regarding bus over- and undervoltage, open loop, overcurrent of pfc and / or inverter, lamp overvoltage (eol1) and rect ifier effect (eol2) (see section 2.5 ) and capacitive loads 1 and 2 (see section 2.6 ). figure 8 shows the lamp voltage versus the frequency durin g the different phases from preheating to the run mode. the lamp voltage rises by the end of the preheating phase with decreasing frequency (e.g., 100 khz to 50 khz) up to, for example, 700 v during ignition. after igni tion, the lamp voltage drops down to its working level with continuous decreasing of the frequency ( figure 8 ) down to its working level e.g. 45 khz (set by a resistor at the rfrun pin to ground). after decreasing of the frequency stops, the ic enters the pre-run mode. figure 7 lamp voltage versus frequency during the different startup phases lamp voltage vs frequency @ different modes 0 100 200 300 400 500 600 700 800 900 1000 10000 100000 frequency [hz] lamp voltage [v] 0 100 200 300 400 500 600 700 800 900 1000 after ignition before ignition ignition after ignition pre run and run mode pre heating operation without load operation with load ICB2FL03G controller for fluorescent lamp ballasts functional description final data sheet 19 v1.1, 2013-08-14 2.3 filament detection duri ng start-up and run mode the low and high side filament detection is sensed via the res and the lvs pins. the low side filament detection during start-up and run mode is detected via the res pin only. an open high side f ilament during start-up will be sensed via the lvs and the res pins. 2.3.1 start-up with brok en low side filament a source current of i res3 = -21.3 a from the res pin (13) monitors the exis tence of a low side filament during a start-up (also in run mode). in the case of an open lo w side filament during the st art-up hysteresis (10.6 v < v cc < 14.0 v) a capacitor (c19 in figure 3 ) will be charged up via i res3 = -21.3 a. when the voltag e at the res pin (13) exceeds v res1 = 1.6 v, the controller prevents a power up and clamps the res voltage internally at v res = 5.0 v. the gate drives of the pfc and inverter stage do not start working. figure 8 start-up with open low side filament figure 9 restart from open low side filament 21.3a 10.6 v no power up 14.0 v 16.0 v start up hysteresis uvlo chip supply voltage 17.5 v start up with open low side filament time v res 1.3 v 1.6 v 5.0 v v cc time v lamp time time 17.7a i res i res 10.0 v latch mode 16.0 v chip supply voltage 17.5 v restart from open low side filament time v res 1.3 v 1.6 v 5.0 v time time v lamp time power up into run mode pfc gate drive 1 2 3 timer t = 100 ms 21.3a 17.7a ICB2FL03G controller for fluorescent lamp ballasts functional description final data sheet 20 v1.1, 2013-08-14 the ic comparators are then set to a threshold of v res1 = 1.3 v and to i res4 = - 17.7 a, the controller waits until the voltage at the res pin drops below v res1 = 1.3 v. when a filament is present ( figure 9 , section 2), the voltage drops below 1.3 v and the value of the source current out of the res pin is set from i res4 = -17.7 a up to i res3 =-21.3 a. the controller then powers up the system, including soft start and preheating, into the run mode. 2.3.2 low side filament detection during run mode in the case of an open low side filament during run mode, the current flowing out of the res pin i res3 = -21.3 a charges up the capacitor c19 in figure 3 . if the voltage at the res pin exceeds the v res3 = 3.2 v threshold, the controller detects an open low side filament and stops the gate drives after a delay of t = 620 s of an internal timer. figure 10 open low side filament run mode figure 11 restart from open ls filament v cc / v pfcgd time 10.0 v 16.0 v f a u l t e v e n t chip supply voltage 17.5 v open low side filament during run mode time v res 1.3 v 3.2 v 5.0 v time time v lamp 21.3a i res pfc gate drive delay t = 620s 17.7a 1.6 v latch mode i res 10.0 v latch mode 16.0 v chip supply voltage 17.5 v restart from open low side filament time v res 1.3 v 1.6 v 5.0 v time time v lamp time power up into run mode pfc gate drive 1 2 3 timer t = 100 ms 21.3a 17.7a ICB2FL03G controller for fluorescent lamp ballasts functional description final data sheet 21 v1.1, 2013-08-14 a restart is initiated when a filament is detected e.g. in the case of a lamp removal. if a filament is present ( figure 11 , section 2), the voltage drops below 1.3 v and the va lue of the source current flowing out of the res pin is set from i res4 = -17.7 a up to i res3 =-21.3 a. the controller powers up the system, including soft start and preheating, into the run mode ( figure 11 , section 3). 2.3.3 start-up with bro ken high side filament an open high side filament during the start-up hysteresis (10.6 v < v cc < 14.0 v) is detected when the current into the lvs pin 12 is below i lvs = 12 a (typically). in that case, the current flowing out of the res pin 13 rises up to i res1 = -42.6 a. this causes the voltage at the res pin to cross v res1 = 1.6 v. the source current is now set to i res2 = -35.4 a and another threshold of v res2 = 1.3 v is active. the controller prevents a power-up (see figure 12 ), and the gate drives of the pfc and inverter stage do not start working. figure 12 start-up with open high side filament i res 10.6 v no power up 14.0 v 16.0 v start up hysteresis uvlo chip supply voltage 17.5 v start up with open high side filament time v res 1.3 v 1.6 v v cc time time 42.6a 35.4a 21.3a v lamp i res time 17.7a 2.0 v time i lvs 12a i lvs ICB2FL03G controller for fluorescent lamp ballasts functional description final data sheet 22 v1.1, 2013-08-14 figure 13 restart from open high side filament when the high side filament is presen t, e.g. insertion of a lamp, the current of the active lvs pin exceeds i lvs > 12 a (typically), the res current drops from i res2 = -35.4 a down to i res4 = -17.7 a ( figure 13 ). the controller then senses the low side filament. if a low side filament is also present, and the controller drops (after a short delay due to a capacitor at the res pin) below v res2 = 1.3 v, the res current is set to i res3 = -21.3 a, and the controller powers up the system. 10.6 v no power up 14.0 v 16.0 v chip supply voltage 17.5 v restart from open high side filament time v res 1.3 v 1.6 v 2.0 v v cc time time i res v lamp i res time power up (into run mode) time i lvs i lvs 12a 42.6a 35.4a 21.3a 17.7a ICB2FL03G controller for fluorescent lamp ballasts functional description final data sheet 23 v1.1, 2013-08-14 2.4 pfc preconverter 2.4.1 discontinuous conduction and cr itical conduction mode operation the digitally controlled pfc preconverter starts wit h an internally fixed on time of typically t on = 4.0 s and a variable frequency. the on time is increased every 280 s (typical) up to a maximum on time of 24 s. the control switches practically immediat ely from the discontinuous conduction mode (dcm) to critical conduction mode (critcm) as soon as a sufficient zcd signal beco mes available. the frequency range in critcm is 22 khz to 500 khz depending on the power ( figure 14 ), with a variation of the on time from 24 s > t on > 0.5 s. figure 14 operating frequency and on time versus power in dcm and critcm operation for lower loads (p outnorm < 8 % from the normalized load 1) ) the control operates in discontinuous conduction mode (dcm) with an on time from 4.0 s and increasing off time. the frequency during dcm is variable in a range from 144 khz down to typically 22 khz @ 0.1 % load ( figure 14 ). with this control method, the pfc converter enables stable operation from 100 % load down to 0.1 %. figure 14 shows the on time range in dcm and critcm (critical conduction mode) operation. in the overlapping area of critcm and dcm there is a hysteresis of the on time which causes a negligible frequency change. 2.4.2 pfc bus voltage sensing overvoltage, open loop, bus 95 % and undervoltage states ( figure 15 ) of the pfc bus voltage are sensed at the pfcvs pin via the network r14, r15, r20 and c11 ? figure 3 (c11 acts as a spike suppression filter). 1) normalized power @ low line input voltage and maximum load discontinuous conduction mode (dcm) <> critical condution mode (critcm) 0,01 0,10 1,00 10,00 100,00 1000,00 0,01 0,10 1,00 10,00 100,00 normalized output power [%] pfc frequency [khz] 50% duty cycle 0,10 1,00 10,00 100,00 pfc - on time [s] frequency dcm frequency critcm ton dcm ton critcm frequency @ dcm operation frequency @ critcm operation on time @ critcm operation on time @ dcm operation on time hysteresis in run mode on time hysteresis pre heating increasing power decreasing power light load nominal load ICB2FL03G controller for fluorescent lamp ballasts functional description final data sheet 24 v1.1, 2013-08-14 2.4.2.1 bus overvoltage and pfc open loop the bus voltage loop control is completely integrated ( figure 16 ) and provided by an 8-bit sigma/delta a/d converter with a typical sampling rate of 280 s and resolution of 4 mv/bit. after leaving phase 2 (monitoring), the ic starts power-up (v cc > 14.0 v). after power-up, the ic senses the bus voltage below 12.5 % (open loop) or above 105 % (bus overvoltage) for 130 s. in the case of bus overvoltage (v busrated > 109 %) or open loop (v busrated < 12.5 %) in phases 3 to 8, the ic shuts off the gate drives of the pfc within 5 s or 1 s respectively. in this case, the pfc restarts au tomatically when the bus voltage is within the corridor (12.5 % < v busrated < 105 %) again. is the bus voltage valid after 130 s, the bus voltage sensi ng is set to 12.5 % < v busrated < 109 %. if these thresholds are exceeded for longer than 1 s (open loop) or 5 s (overvoltage), the pfc gate drive stops working until the voltage drops below 105 % or exceeds the 12.5 % level. if the bus overvoltage (> 109 %) lasts for longer than 625 ms in run mode, the inverter gates also shut off and a power-down with complete restart is attempted ( figure 15 ). figure 15 pfc bus voltage operating level and error detection 2.4.2.2 bus voltage 95 % and 75 % sensing when the rated bus voltage is in the corridor of 12.5 % < v busrated < 109 %, the ic will check whether the bus voltage exceeds the 95 % threshold ( figure 15 , phase 3) within 80 ms before en tering the soft start phase 4. another threshold is activated when th e ic enters the run mode (phase 8). if the rated bus voltage drops below 75 % for longer than 84 s, a power-down with a complete restart is attempted when a counter exceeds 800 ms. in the case of short-term bus undervoltage (the bus volt age reaches its working level in run mode before exceeding typically 800 ms (min. 500 ms)) the ic skips phases 1 to 5 and star ts with ignition (see section 2.7.1 for conditions for emergency lighting). the internal reference level of the bus voltage sense v pfcvs is 2.5 v (100 % of the rated bus voltage) with a high accuracy. a surge protection is activated in the case of a rated bus voltage of v bus > 109 % and a low side current sense voltage of v lscs > 1.6 v in pre-run mode, or v lscs > 0.8 v in run mode for longer than 500 ns. bus over voltage: stops pfc gate drive within 5s auto restart when v br < 109 % / t > 625ms pd v br < 105% ? fault u under voltage v br < 75% t < 800ms ar without preheating t > 800ms ar with preheating pfc open loop / keeps all gate drives within 1s auto restart / t > 1s stops pfc fet till v br > 12.5% ? ar mode / time soft start preheating ignition pre-run run mode into normal operation rated bus voltage v br 100 % v bus >95% 1 2 3 5 4 6 7 8 95 % 30 % 60ms 35ms 80ms 11ms 0 - 2500 ms 40 - 237ms 625ms 105 % 75 % 12.5 % 0% typical rated bus voltage level v pfcvs = 2.625v v pfcvs = 2.500v v pfcvs = 2.375v v pfcvs = 1.875v v pfcvs = 0.313 v error corridor ar = auto restart pd = power down cbc = cycle by cycle v br < 95% v cc < 10.6 v v cc < 14.1 v 109 % v pfcvs = 2.725v 130 s ICB2FL03G controller for fluorescent lamp ballasts functional description final data sheet 25 v1.1, 2013-08-14 2.4.3 pfc structure of mixed signals a digital notch filter elimin ates the input voltage ripple independently of the mains frequency. a subsequent error amplifier with pi characteristic ensures st able operation of the pfc preconverter ( figure 16 ). figure 16 structure of the mixed digital and analog control of the pfc preconverter the zero current detection (zcd) is sensed by the pfczcd pin via r13 ( figure 3 ). notification of finished current flow during demagnetization is required in critcm and in dcm also. the input is equipped with a special filtering system, including blanking of typically 500 ns and a large hysteresis of typi cally 0.5 v and 1.5 v v pfczcd ( figure 16 ). 2.4.4 thd correction via zcd signal an additional feature is the thd correction ( figure 16 ). in order to optimize the im proved thd (especially in the zones a shown in figure 17 zcd @ ac input voltage), th ere is a possibility to extend the pulse width of the gate signal (blue part of the pfc gate signal in figure 17 ) with the variable pfc zcd resistor (see resistor r13 in figure 3 ) in addition to the gate signal controlled by the v pfcvs signal (gray part of the pfc gate signal in figure 17 ). ? -adc notch filter under voltage 75% over voltage 109% open loop 12.5% pi loop control pwm over current 1v 5.0% zcd start up 1.5v / 0.5v clock 870 khz gate drive pfcvs pfcgd pfccs pfczcd int. reference v pfcvs = 2.5 v thd correction bus voltage 95% ICB2FL03G controller for fluorescent lamp ballasts functional description final data sheet 26 v1.1, 2013-08-14 figure 17 thd optimization using adjustable pulse width extension in the case of dc input voltag e (see dc input voltage in figure 17 ), the pulse width gate signal is fixed as a combination of the gate signal controlled by the v pfcvs pin (gray) and the additional pulse width signal controlled by the zcd pin (blue) shown in figure 17 zcd @ dc input voltage. the pfc current limitation at pin pfccs interrupts the on time of the pfc mosfet if the voltage drop at the shunt resistors r18 ( figure 3 ) exceeds v pfccs = 1.0 v ( figure 16 ). this interrupt will restart after the next sufficient signal from zcd becomes available (auto restar t). the first value of the re sistor can be calculated by the ratio of the pfc mains choke and zcd winding by the bus voltage and a current of typically 1.5 ma (see equation below for a good practical value of resistance of zcd). an adjustment of the zcd resistor causes an optimized thd. 2.5 detection of end-of-l ife and rectifier effect two effects are present by end of life (eol): lamp overvoltage (eol1) and a rectifier effect (eol2). after ignition (see 1 in figure 18 ), the lamp voltage breaks down to its ru n voltage level with decreasing frequency. on reaching the run frequency, the ic enters the pre-run mode for 625 ms. during this period, the eol detection is still disabled. in the su bsequent run mo de (2 in figure 18 ) the detection of eol1 (lamp overvoltage; see 3, figure 18 ) and eol2 (rectifier effect; see 4, figure 18 ) is enabled completely. rectified ac input voltage 0 voltage at zcd-winding dc input voltage 0 0 pfc gate drive voltage a b a zcd @ dc input voltage zcd @ ac input voltage pfc gate signal (gray) controlled by the v pfcvs pfc gate signal (blue) controlled by the zcd ma v n n r bus pfc zcd zcd 5 . 1 * = ICB2FL03G controller for fluorescent lamp ballasts functional description final data sheet 27 v1.1, 2013-08-14 figure 18 end of life and rectifier effect 2.5.1 detection of end of life 1 (eol1) ? lamp overvoltage the event of eol1 is detected by meas uring the positive and negative peak levels of the lamp voltage via an ac current fed into the pin lvs ( figure 19 ). this ac current is fed into the lvs pins via the network r41, r42, r43, r44 and the low pass filter c40 and r45 ? see figure 3 . if the sensed ac current exceeds 210 a pp for longer than 620 s, the status of end-of-life (eol1) is detected (lamp overvoltage/overload; see figure 19 lvsac current). the eol1 fault results in a latched power-dow n mode (after trying a single restart). the controller continuously monitors the status until the eol1 status changes ? e.g. a new lamp is inserted. figure 19 end of life (eol1) detection, lamp voltage versus ac lvs current t pos. ac level for eol 1 detection 0 neg. ac level for eol 1 detection lamp voltage negative dc level for eol2 detection eol2 rectifier effect eol1 lamp overvoltage normal operation ignition pos. ignition level neg. ignition level 1 2 3 4 positive dc level for eol2 detection t 0 lamp voltage eol1 lamp overvoltage normal operation 3 2 105a peak 0 lvsac current 3 2 eol1 detection t = 620 s pos. ac level for eol1 detection neg. ac level for eol1 detection t t - 105a peak ICB2FL03G controller for fluorescent lamp ballasts functional description final data sheet 28 v1.1, 2013-08-14 2.5.2 detection of end of life 2 (eol2) ? rectifier effect the rectifier effect (eol2) is detecte d by measuring the positive and negativ e dc levels of the lamp voltage via a current fed into the lvs pin ( figure 20 ). this current is fed into the lvs pin via the network r41, r42, r43 and r44 (see figure 3 ). if the sensed dc current exceeds 42 a ( figure 20 lvsdc current) for longer than 2500 ms, the status of end-of-life (eo l2) is detected. the eol2 fault results in a latched power-down mode (after trying a single restart) and the controller is continuously monitoring. the insertion of a new lamp or an interruption of the input voltage resets the status of the ic. figure 20 end of life (eol2) detection, lamp voltage versus dc lvs current 2.6 detection of capacitive load in order to prevent a malfunction in the area of capacitive load (see figure 21 ) during run mode due to certain deviations from the normal load (e.g. harmed lamp, sudden break of the lamp tube ?), the ic has three integrated thresholds ? sensed only via the lscs (pin 2). the controller distinguishes between two different states of capacitive load: detection of working without load (idling detection, capload 1) and working with short overcurrent (capload 2). this state (capload 2) affects operatio n below the resonance in the capacitive load area ( figure 23 ). in both cases, the ic results in a latched power- down mode after a single restart. after latching the power-down mode, the controller continuously monitors th e input voltage and lamp fila ments, and restarts after interruption of the input voltage or insertion of a new lamp. pos. dc level for eol2 detection 0 lamp voltage normal operation 2 eol2 rectifier effect t 4 42 a 0 t lvsdc current -42 a neg. dc level for eol2 detection eol2 detection t = 2500 ms ICB2FL03G controller for fluorescent lamp ballasts functional description final data sheet 29 v1.1, 2013-08-14 figure 21 capacitive and inductive operation 2.6.1 capacitive load 1 (idling det ection ? current mode preheating) a capacitive load 1 operation (idling) is detected wh en the voltage at the lscs pin is below +50 mv during the second 50 % on time of the low side mosfet (see capacitive load 1 (idling) in figure 22 ). if this status is present for longer than 2500 ms, the controller triggers a latched power-down mode after trying a single restart. the controller keeps monitoring t he status continuously until an adequate load is present (e.g. lamp removal); then the ic changes to normal operation. figure 22 capacitive mode 1 operation without load during run mode lamp voltage vs frequency @ different modes 0 100 200 300 400 500 600 700 800 900 1000 10000 100000 frequency [hz] lamp voltage [v] 0 100 200 300 400 500 600 700 800 900 1000 after ignition before ignition ignition after ignition pre run and run mode pre heating area of capacitive load behavior load area of inductive load behavior v dsls v gatehs v lscs capacitive load 1 (idling) t capload 1 + 50 mv i dsls v gatels v dsls v gatehs v lscs normal operation t capload 2 + 50 mv i dsls v gatels t capload 1 2nd 50% on time 2nd 50% on time capacitive load 1 operation (ballast with current mode preheating) ICB2FL03G controller for fluorescent lamp ballasts functional description final data sheet 30 v1.1, 2013-08-14 2.6.2 capacitive load 2 (overcurrent / operation below resonance) a capacitive load 2 operation is dete cted if the voltage at the lscs pi n drops below a second threshold of v lscs = ?50 mv directly before the high side mosfet is turned on or exceeds a third threshold of v lscs = 2.0 v during on switching of the high si de mosfet. if this overcurrent is present for longer than 620 s, the ic triggers a latched power-down mode after trying a single restart. the controller keeps monitoring the status continuously until an adequate load is present e.g. a new lamp is inserted; then the ic changes to normal operation. figure 23 capacitive mode 2 ? operation with overcurrent 2.6.3 adjustable self-adapting dead time the dead time between the turn off and turn on of the half-bridge drivers is adjustable (c16, see figure 3 ) and is detected via a second threshold (?50 mv) of the lscs voltage. the range of the dead time adjustment is 1.05 s up to 2.1 s during all operating modes. the start of the dead time measurement is the off switching of the high side mosfet. the end of the dead time measurement is when v lscs drops for longer than typically 200 ns (internal fixed propagation delay) belo w ?50 mv. this time will be stored (s tored dead time) and the low side gate driver switches on. the high side gate driver turns on again after off switching of the low side switch and the stored dead time. figure 24 dead time of on and off of the half-bridge drivers v dsls v gatehs v lscs + 2.0 v capacitive load 2 (over current ) t capload 2 - 50 mv i dsls v gatels v dsls v gatehs v lscs + 2.0 v normal operation t capload 2 - 50 mv i dsls v gatels v dsls gate hs normal operation in run mode v lscs gate ls stored dead time 200 ns propagation delay dead time stored dead time dead time v lscs = -50mv start of dead time measurement end of dead time measurement ICB2FL03G controller for fluorescent lamp ballasts functional description final data sheet 31 v1.1, 2013-08-14 2.7 emergency lighting line interruptions (bus voltage drops) are detected by the pfcvs. if the rated pfc bus voltage drops below v busrated < 75 % during run mode, the controller detects pfc bus undervoltage. in order to meet the emergency lighting standards, the controller distinguishes between tw o different states of pfc bus undervoltage: short- and a long-term pfc bus undervoltage. a timer increases the time as long as bus undervoltage is present. short-term bus undervoltage is detected if the ti mer value stays below t < 800 ms typical (500 ms min.) after the bus voltage reaches the nominal level again. this causes a restart without preheating (e mergency standard of vde0108) ? see figure 25 . if the timer exceeds t > 800 ms, the controller forces a complete restart of the system due to long- term bus undervoltage ( figure 26 ). 2.7.1 short-term pfc bus undervoltage short-term pfc bus undervoltage ( figure 25 ) is detected if the duration of the undervoltage does not exceed 800 ms (timer stays below t < 800 ms, see figure 25 ). in that case, the pfc and in verter drivers are immediately switched off and the controller continuously monitors the status of the bus voltage in a latched power-down mode (i cc < 170 a). if the signal at the lvs pin exceeds 18 a and the rated bus voltage is above 12.5 % while the timer is below t < 800 ms, the controller restarts from power up without preheating. the timer resets to 0 when entering run mode. figure 25 bus voltage drop below 75% (rated bus voltage) for t < 800 ms during run mode bus voltage drop for t < 800 ms restart without preheating 100% 75% v busrated v cc 16v i preheating v lamp i cc < 6 ma + i qgate < 160 a < 6 ma + i qgate interrupt for t < 800 ms timer t = 800ms run mode power down mode ignition pre run run mode ICB2FL03G controller for fluorescent lamp ballasts functional description final data sheet 32 v1.1, 2013-08-14 2.7.2 long-term pfc bus undervoltage if the duration of the bus undervoltage exceeds t > 800 ms (see figure 26 ), the controller forces an undervoltage lockout (uvlo). the chip supply voltage drops below v cc = 10.6 v and the chip supply current is below i cc <130 a. when the vcc voltage exceeds the 10.6 v thresh old again, the ic current consumption is below i cc <160 a. in that case, the controller resets the timer and restarts with the full start-up procedure, including monitoring, power-up, start-up, soft start, preheatin g, ignition, pre-run and run modes, as shown in figure 26 . figure 26 bus voltage drop below 75% (rated bus voltage) for t > 800 ms during run mode 2.8 built-in customer test mode operation in order to decrease the final ballast testing time for customers, the 2nd generation of ballast ic supports an integrated built-in customer test mode and several func tions to disable some features and states of the ic. 2.8.1 preheating test mode this feature forces the ic to stay in the preheating mode (see section 2.8.1.2 ) or to start ignition immediately without any preheating (see section 2.8.1.1 ). a resistor at this pin defines the duration of the preheating phase. normally, the preheating phase is in a range of 0 ms up to 2500 ms set via a resistor r rtph = 0 ? up to 25 k ? from the rtph pin to gnd. the preheating phase is skipped when the rthp pin is set to gnd. if the signal at this pin is v rtph > 5.0 v, the ic remains in the preheating mode. 95% 75% v busrated v cc 16v i preheating v lamp i cc < 6 ma + i gate < 160 a < 6 ma + i gate interrupt for t > 800 ms timer t = 800ms uvlo @ 10.6v bus voltage drop for t > 800 ms restart with full start procedure run mode power down mode uvlo monitoring power up start up s oft start ignition pre run run mode preheating <160 a ICB2FL03G controller for fluorescent lamp ballasts functional description final data sheet 33 v1.1, 2013-08-14 2.8.1.1 skip the preheating ph ase ? set rtph pin to gnd figure 27 shows a standard start-up with a preheating time se t via resistor at the rtph pin 11 to gnd (e.g. 8.2 k ? ? this is equal to a preheating phase of approx. 820 m s). the preheating phase can be skipped by setting the rtph pin 11 directly to gnd. in th is case, ignition takes place directly after the soft start phase (see figure 28 ). figure 27 start-up with preheating figure 28 start-up without preheating 10.6 v 14.0 v 16.0 v start up hysteresis uvlo chip supply voltage 17.5 v time v rtph 2.5 v 5.0 v v cc time time 10.0 v v lsgd v lamp time pre heating standard start up with pre heating duration of pre heating is set by resistor only t = 820 ms when using r rtph = 8.2kohm start up without pre heating v lsgd 10.6 v 14.0 v 16.0 v start up hysteresis uvlo chip supply voltage 17.5 v time v rtph 2.5 v 5.0 v v cc time time 10.0 v v lamp time ingnition directly set rtph resistor to gnd ICB2FL03G controller for fluorescent lamp ballasts functional description final data sheet 34 v1.1, 2013-08-14 2.8.1.2 ic remains in preheating phase this feature gives the customer the flexibility to alig n the preheating fr equency to the fila ment power in the preheating phase. figure 29 shows a standard start-up with the set preheating time of, for example, 820 ms with an 8.2 k ? resistor at the rtph pin 11. to force the ic to rema in in preheating, the voltage level at the rtph pin 11 has to be set to 5.0 v. the duration of this 5.0 v signal defines the time of the preheating (see i preheat in figure 30 ). figure 29 start-up with preheating figure 30 start-up without preheating 10.6 v 14.0 v 16.0 v start up hysteresis uvlo chip supply voltage 17.5 v time v rtph 2.5 v v cc time v lamp time i preheat time preheating t = 820 ms when using rrtph = 8.2kohm ignition duration is set by resistor only 5.0 v v rtph i preheat 10.6 v 14.0 v 16.0 v start up hysteresis uvlo chip supply voltage 17.5 v time 5.0 v v cc time v lamp time time ic remains in preheating no ignition set by external 5.0v signal 2.5 v ICB2FL03G controller for fluorescent lamp ballasts functional description final data sheet 35 v1.1, 2013-08-14 2.8.2 deactivation of th e filament detection in order to deactivate the filament detection of the low or high side filament, set the res pin 13 or the lvs pin to gnd. in this case, the ic starts up in normal operat ion without checking the filaments ? e.g. when using an equivalent lamp resistive load instead of a load. figure 31 deactivation via res pin figure 32 deactivation via lvs pin figure 31 shows the deactivation of the low and high si de filament via set the res pin 13 to gnd. figure 32 shows the deactivation of the high side fila ment detection via set the lvs pin to gnd. note: an unused lvs pin has to be set to gnd. v lsgd 10.6 v 14.0 v 16.0 v start up hysteresis uvlo chip supply voltage 17.5 v time v res 1.3 v 1.6 v 5.0 v v cc time time 10v v lamp time res pin set to gnd time time time 10.6 v 14.0 v 16.0 v start up hysteresis uvlo chip supply voltage 17.5 v v res 1.3 v 1.6 v 5.0 v v cc time v lsgd v lamp lvs pin set to gnd 10v ICB2FL03G controller for fluorescent lamp ballasts functional description final data sheet 36 v1.1, 2013-08-14 2.8.3 built-in customer test mode (clock acceleration) the built-in customer test mode, supported by this ic, save s testing time for customers in terms of ballast end test. in this mode, the ic accelerates the internal clock in order to reduce the time of the 4 different procedures by the following factors (see table 2 ). 2.8.3.1 enabling of th e clock acceleration the clock acceleration (bu ilt-in customer test mode) is activated when the chip supply voltage exceeds v cc > 14.0 v and the voltages at the run and preheating frequency pins are set to v rfrun = v rfph = 5.0 v ( 5 %) ? see figure 33 . a res pin voltage of v res > 3.5 v up to 5.0 v ( 5 %) prevents a power-up of the ic, the ic remains in a mode before powering up as long as the voltage at the res pin is v res > 3.5 v up to 5.0 v ( 5 %) ? no power- up. note: after the activation of the clock acceleration mode, the voltage level of 5.0 v at the run and preheating frequency pins (v rfrun = v rfph ) can be released. 2.8.3.2 starting the chip with accelerated clock in order to start the ic with an accelerated cl ock, set the voltage at the res pin to gnd (v res = 0 v), see figure 33 . the ic powers up the system and starts working with an accelerated clock. the duration of the different modes are accelerated by the factors shown in table 2 . figure 33 clock acceleration (built in customer test mode) table 2 specified acceleration factors phase duration for test [ms] acceleration factor nominal duration [ms] preheating 625 4 2500 (max) time out ignition 118.5 2 237 pre run mode 41.7 15 625 eol2 41.7 60 2500 v rfph 10.6 v 14.0 v time v rfrun 2.5 v 5.0 v v cc time time 2.5 v 5.0 v enabling of clock acceleration starting the chip with an accelerated clock v res 3.5 v time v ccnom ic remains in power up filament detection ic powers up accelerated pre heating by factor 4 accelerated pre run by factor 15 accelerated ign. time out by factor 2 accelerated eol2 by factor 60 in run mode propagation delay ICB2FL03G controller for fluorescent lamp ballasts state diagram final data sheet 37 v1.1, 2013-08-14 3 state diagram 3.1 features during diff erent operating modes figure 34 monitoring features during different operating modes 0...80ms start -up 10ms softstart 10.6v < vcc < 17.5v f= f_ph 0...2500ms preheating 40...237 ms ignition 625 ms pre-run run 10.6v < vcc < 17.5v f= f_run mains switch turned on; 0v < vcc < 10.6v; i_vcc < 130a; i_res= 0a typ. 35ms monitoring typ . 60ms uvlo bus overvoltage > 109% bus undervoltage < 75% bus open loop < 12,5% overcurrent pfc overcurrent inverter capacitive load 2 eol 1, overload eol 2, rectifier effect enabled pfc enabled pfc enabled enabled 1,6v enabled enabled 1,6v enabled enabled 0,8v enabled enabled enabled pfc 5s enabled inv 625 ms enabled 84s enabled 200 ns threshold 1.0v enabled 620s u u u n f f a = auto restart n = no fault u = undervoltage f = fault, a single restart minimum duration of effect vcc > 14.0v & filament detected; 12,5%< vbus <105% => start after 130s f_start = 135khz as long as vbus < 95% f f 10.6v < vcc < 17.5v vbus > 95% f_start > f > f_ph 10.6v < vcc < 17.5v f_ph > f > f_run enabled pfc 10.6v < vcc < 17.5v; i_res= 21.3a; f= f_run 10.6v < vcc < 14.0v; i_vcc < 160a; i_res= 21.3a fault: 10.6v < vcc < 17.5v; i_vcc < 170a; i_res= 21.3a disabled by lamp removal or uvlo f= a single restart is possible after delay of 200ms by internal timer enabled 2,5s bus undervoltage < 95% a enabled pfc enabled pfc enabled pfc enabled pfc enabled pfc enabled pfc enabled enabled 1,6v enabled 1,6v enabled 500ns threshold 0.8v enabled 620s bus overvoltage > 105% a enabled 130s enabled pfc 5s enabled inv 625 ms enabled pfc enabled 2,5s capacitive load 1 f ICB2FL03G controller for fluorescent lamp ballasts state diagram final data sheet 38 v1.1, 2013-08-14 3.2 operating flow of the star t-up procedure into run mode figure 35 operating flow during start-up procedure after 130s & v bus > 12,5% & v bus < 105% vcc > vccon (14.0v ) & filament detected v bus > 95% within 80ms vcc > 10.6v v bus < 12,5% or v bus > 105% after 10ms & flag skip preheat = reset after t_ph= 0...2500ms time set by r_tph f_inv= f_run within t_ign= 40...237ms after t_prerun= 625ms uvlo vcc < 10.6v icc < 130a monitoring vcc > 10.6v icc < 160a power-up gate drives off 14.1v < vcc icc approx 6.0ma start-up inverter gates on pfc gate on 17.5v> vcc >10.6v f_inv = f_start softstart 17.5v> vcc >10.6v f_start=> f_ph preheat 17.5v> vcc >10.6v f = f_ph ignition* timeout 237ms 17.5v> vcc >10.6v f_ph => f_run pre-run 17,5v> vcc >10.6v f = f_run reduced monitoring run 17.5v> vcc >10.6v f = f_run complete monitoring after 10ms & flag skip preheat = set // reset flag skip preheat & counter skip ph // fault 17.5v> vcc >10.6v icc < 170a gate drives off see protection functions see timing and handling of fault conditions * note: ignition will reset the flag skip preheating vcc < 10.6v ICB2FL03G controller for fluorescent lamp ballasts state diagram final data sheet 39 v1.1, 2013-08-14 3.3 auto restart and latc hed fault condition mode figure 36 operating process during start-up mode and handling of fault conditions fault a auto restart surge; time out start up (vbus < 95% for t > 80 ms) fault f fault, single restart open filament ls; inverter overcurrent; capacitive load 1; capacitive load 2; timeout ignition; eol 1 (overload); eol 2 (rectifier effect); fault u bus voltage bus undervoltage (vbus < 75% during run mode for t > 84s); bus overvoltage (vbus > 109% for t > 625ms); increment fault counter set flag skip preheat inverter and pfc gate off only at inverter over current pfc gate off appr. 150s delayed power down icc < 160a wait 200ms delay timer a fault counter < 2 increment counter skip ph gate drives off ic remains in active mode counter skip preheat >7? power-up gate drives off y n y n n y gate drives off power down icc < 160a wait 100ms delay timer a vcc < 10.6v? n y note: fault counter reset after 40s in run mode reset of flag skip preheat after ignition vcc > 14.0v? wait for lamp removal lamp removed for min 100ms lamp inserted for min 100ms y n fault a timeout 80ms start-up start start-up inverter gates on pfc gate on 17.5v> vcc >10.6v f_inv = f_start y n t > 80ms? from power-up end start-up wait for lamp inserted lamp inserted? n y uvlo reset all latches n y reset flag skip preheat & counter skip ph reset fault counter wait for uvlo v bus > 95%? note to set flag skip preheat: when using external vcc supply, no reset of set flag skip preheat. 1st restart without preheating while vcc > uvlo. when lvs deactivated or not from line. note for external vcc supply, set vcc below uvlo. lamp inserted & i lvssink > 12a typ. ICB2FL03G controller for fluorescent lamp ballasts protection functions matrix final data sheet 40 v1.1, 2013-08-14 4 protection functions matrix table 3 protection functions matrix description of fault characteristics of fault operating mode detection active consequence name of fault type of fault minimum duration of effect monitoring power-up 130 s start-up until v bus > 95% softstart 10ms preheat mode 0 ? 2500ms ignition mode 40 ? 237ms pre-run mode 625ms run mode supply voltage v cc < 14.0 v before power-up below start- up threshold s1 s x prevents power-up supply voltage v cc < 10.6 v after power-up below uvlo threshold s5 s xxxxxxxxpower-down, reset failure latch current into lvs pin < 12 a (typ.) before power-up open filament hs s100 s x prevents power-up voltage at res pin > 1.6 v before power-up open filament ls s100 s x prevents power-up voltage at res pin > 3.2 v open filament ls f620 s x power down, latched fault mode, 1 restart bus voltage < 12.5% of rated level 10 s after power-up open loop detection s1 s x keep gate drives off, re- start after v cc hysteresis bus voltage < 12.5 % of rated level open loop detection n1 s xxxxxxstops pfc fet until v bus > 12.5% bus voltage < 12.5% of rated level shut-down option u 625ms x power down, restart when v bus > 12.5% bus voltage < 75% of rated level add. shut down delay 120 s under- voltage u84 s x power down, 100ms delay, restart, skip pre- heating max 7 times bus voltage < 95% of rated level during start-up timeout max start-up time a 80ms x power down, 200ms delay, restart bus voltage > 105% of rated level 10 s after power-up over- voltage s5 s x keep gate drives off, re- start after vcc hysteresis bus voltage > 109% of rated level in active operation pfc overvoltage n5 s xxxxxxstops pfc fet until v bus < 105% bus voltage > 109% of rated level in active operation inverter overvoltage u 625ms x power down, restart when v bus <105% +/- peak level of lamp voltage at pin lvs above threshold eol 1 overvoltage f620 s x power down, latched fault mode, 1 restart dc level of lamp voltage above +/- threshold eol 2 rect. effect f 2500ms x power down, latched fault mode, 1 restart capacitive load 1 cap load 1 idling f 2500ms x power down, latched fault mode, 1 restart capacitive load 2, operation below resonance cap. load 2 overload f620 s x power down, latched fault mode, 1 restart ICB2FL03G controller for fluorescent lamp ballasts protection functions matrix final data sheet 41 v1.1, 2013-08-14 run frequency cannot be achieved timeout ignition f 237ms x power down, latched fault mode, 1 restart voltage at pfccs pin >1.0 v pfc overcurrent n 200ns xxxxxxstops on-time of pfc fet immediately voltage at lscs pin >0.8v inverter current lim n 200ns x activates ignition control voltage at lscs pin >0.8v inverter overcurrent f 500ns x x power down, latched fault mode, 1 restart voltage at lscs pin >1.6v inverter overcurrent f 500ns x x x x power down, latched fault mode, 1 restart inverter overcurrent & vbus > 109% (surge) surge a 500ns x x power-down, restart when v bus < 109 % after jump into latched fault mode f wait 200ms a single restart attempt after delay of internal timer reset of failure latch in run mode after 40s reset of failure latch by uvlo or 40 s in run mode s = start-up condition, n = no fault, a = auto restart , u = undervoltage f = fault with a single restart; a second f leads to a latched fault note: all values @ typical 50 hz mains frequency table 3 protection functions matrix (cont?d) description of fault characteristics of fault operating mode detection active consequence name of fault type of fault minimum duration of effect monitoring power-up 130 s start-up until v bus > 95% softstart 10ms preheat mode 0 ? 2500ms ignition mode 40 ? 237ms pre-run mode 625ms run mode ICB2FL03G controller for fluorescent lamp ballasts electrical characteristics final data sheet 42 v1.1, 2013-08-14 5 electrical characteristics all voltages without the high side signals are measured wit h respect to ground (pin 4). the high side voltages are measured with respect to pin 17. the voltage leve ls are valid if other ratings are not violated. 5.1 absolute maximum ratings absolute maximum ratings are defined as ratings, which when exceeded may lead to destruction of the integrated circuit. for the same reason, ensure that any capacitor to be connected to pin 3 (v cc ) or pin 15 (hsv cc ) is discharged before assembling the application circuit. parameter symbol limit values unit remarks min. max. lscs voltage v lscs ?5 6 v lscs current i lscs ?3 3 ma lsgd voltage v lsgd ?0.3 v cc +0.3 v internally clamped to 11 v lsgd peak source current i lsgdsomax ?75 5 ma < 500 ns lsgd peak sink current i lsgdsimax ?50 400 ma < 100 ns vcc voltage v vcc ?0.3 18.0 v vcc zener clamp current i vcczener ?5 5 ma ic in power down mode pfcgd voltage v pfcgd ?0.3 v cc +0.3 v pfcgd peak source current i pfcgdsomax ?150 5 ma < 500 ns pfcgd peak sink current i pfcgdsimax ?100 700 ma < 100 ns pfccs voltage v pfccs ?5 6 v pfccs current i pfccs ?3 3 ma pfczcd voltage v pfczcd ?3 6 v pfczcd current i pfczcd ?5 5 ma pfcvs voltage v pfcvs ?0.3 5.3 v rfrun voltage v rfrun ?0.3 5.3 v rfph voltage v rfph ?0.3 5.3 v rtph voltage v rtph ?0.3 5.3 v res voltage v res ?0.3 5.3 v lvs voltage v lvs ?6 7 v lvs current1 i lvs_1 ?1 1 ma ic in power down mode lvs current2 i lvs_2 ?3 3 ma ic in active mode hsgnd voltage v hsgnd ?650 650 v referring to gnd 1) hsgnd voltage transient dv hsgnd /dt ?40 40 v/ns hsvcc voltage v hsvcc ?0.3 18.0 v referring to hsgnd hsgd voltage v hsgd ?0.3 v hsvcc + 0.3 v internally clamped to 11v hsgd peak source current i hsgdsomax ?75 0 ma < 500 ns hsgd peak sink current i hsgdsimax 0 400 ma < 100 ns junction temperature t j ?25 150 c ICB2FL03G controller for fluorescent lamp ballasts electrical characteristics final data sheet 43 v1.1, 2013-08-14 storage temperature t s ?55 150 c maximum power dissipation p tot ?1wpg_dso-16 t amb =25c thermal resistance (both chips) junction-ambient r thja ? 125 2) k/w pg_dso-16 soldering temperature wave ? 260 c wave soldering 3) soldering temperature reflow ? 4) c reflow soldering esd capability hbm v esd_hbm ? 2 kv human body model 5) esd capability cdm v esd_cdm ? 1 kv charged device model 6) rated bus voltage (95%) v pfcvs95 2.33 2.43 v 1) limitation due to voltage capability in end test 2) @ta = 85c & pcb area >30mmx20mm 3) according to jesd22a111 4) according to j-std-020d 5) according to eia/jesd22-a114-b 6) according to jesd22-c101 parameter symbol limit values unit remarks min. max. ICB2FL03G controller for fluorescent lamp ballasts electrical characteristics final data sheet 44 v1.1, 2013-08-14 5.2 operating range the ic operates as described in the functional descripti on once the values listed here lie within the operating range. parameter symbol limit values unit remarks min. max. hsvcc supply voltage v hsvcc v hsvccoff 17.5 v referring to hsgnd hsgnd voltage v hsgnd ?650 650 v referring to gnd 1) 1) limitation due to creeping distance between the hs&ls pins vcc voltage @ 25c v vcc v vccoff 17.5 v t j = 25c vcc voltage @ 125c v vcc v vccoff 18.0 v t j = 125c lscs voltage range v lscs ?4 5 v in active mode pfcvs voltage range v pfcvs 04v pfccs voltage range v pfccs ?4 5 v in active mode pfzcd current range i pfczcd ?3 3 ma in active mode lvs voltage range v lvs ?6 6 2) 2) limited by maximum of current range at lvs v lvs current range i lvs 3) 3) limited by minimum of voltage range at lvs 210 a ic power down mode lvs current range i lvs ?2.5 2.5 ma ic active mode rfph frequency f rfphrange f run 150 khz rfph source current range i rfph ?500 0 a@ v rfph = 2.5 v rtph voltage range v rtph 02.5v junction temperature t j ?25 125 c adjustable preheating freq. f rfph f rfrun 150 khz range set by rfph adjustable run frequency f rfrun 20 120 khz range set by rfrun adjustable preheating time t rtph 0 2500 ms range set by rtph set resistor for run feq. r rfrun 425k ? set resistor for preheat feq. r rfph 4?k ? r rfrun parallel to r rfph set resistor for preheat time r rtph 025k ? mains frequency f mains 45 65 hz notch filter operation ICB2FL03G controller for fluorescent lamp ballasts electrical characteristics final data sheet 45 v1.1, 2013-08-14 5.3 characteristics 5.3.1 power supply section the electrical characteristi cs involve the spread of values guarant eed within the specified supply voltage and junction temperature range t j from ?25 c to +125 c. typical values represent the median values, which are related to 25 c. unless otherwise stated, a supply voltage of 15 v and v hsvcc = 15 v is assumed and the ic operates in active mode. furthermore, all vo ltages refer to gnd if not otherwise stated. parameter symbol limit values unit test conditions min. typ. max. vcc quiescent current1 i vccqu1 ?90130 av vcc = v vccoff ? 0.5v vcc quiescent current2 i vccqu2 ? 120 160 av vcc = v vccon ? 0.5v vcc supply current 1) 1) with inactive gate i vccsupply ?4.26.0mav pfcvs > 2.725v vcc supply curr ent in latched fault mode i vcclatch ? 110 170 av res = 5v lsvcc turn-on threshold lsvcc turn-off threshold lsvcc turn-o n/off hyst. v vccon v vccoff v vcchys 13.5 10.0 3.2 14.0 10.6 3.6 14.5 11.0 4.0 v v v hysteresis vcc zener clamp voltage v vccclamp 15.5 16.3 16.9 v i vcc = 2ma/v res = 5v vcc zener clamp current i vcczener 2.5 ? 5 ma v vcc = 17.5v/v res = 5v high side leakage current i hsgndleak ?0.012 av hsgnd = 650v, v gnd =0v hsvcc quiescent current i hsvccqu1 2) 2) referring to high side ground (hsgnd) ? 190 280 av hsvcc = v hsvccon ? 0.5v hsvcc quiescent current 1) i hsvccqu2 2) 0.30.651.2 mav hsvcc > v hsvccon hsvcc turn-on threshold hsvcc turn-off threshold hsvcc turn-on/off hyst. v hsvccon 2) v hsvccoff 2) v hsvcchy 2) 9.8 8.1 1.4 10.4 8.6 1.7 11.0 9.3 2.0 v v v hysteresis low side ground gnd ICB2FL03G controller for fluorescent lamp ballasts electrical characteristics final data sheet 46 v1.1, 2013-08-14 5.3.2 pfc section 5.3.2.1 pfc current sense (pfccs) 5.3.2.2 pfc zero curr ent detection (pfczcd) parameter symbol limit values unit test conditions min. typ. max. turn ? off threshold v pfccsoff 0.95 1.0 1.05 v over current blanking + propagation delay 1) 1) propagation delay = 50 ns t pfccsoff 140 200 260 ns leading edge blanking t blanking 180 250 310 ns pulse width when v pfccs > 1.0 v pfccs bias current i pfccsbias ?0.5 ? 0.5 av pfccs = 1.5v parameter symbol limit values unit test conditions min. typ. max. zero crossing upper thr. 1) 1) turn off threshold v pfczcdup 1.4 1.5 1.6 v zero crossing lower thr. 2) 2) turn on threshold v pfczcdlow 0.4 0.5 0.6 v zero crossing hysteresis v pfczcdhys ?1.0? v clamping of pos. voltages v pfczcdpclp 4.1 4.6 5.1 v i pfczcdsink = 2ma clamping of neg. voltages v pfczcdnclp ?1.7 ?1.4 ?1.0 v i pfczcdsource = ?2ma pfczcd bias current i pfczcdbias ?0.5 ? 5.0 av pfczcd = 1.5v pfczcd bias current i pfczcdbias ?0.5 ? 0.5 av pfczcd = 0.5v pfczcd ringing su. 3) time 3) ringing suppression time t ringsup 350 500 650 ns limit value for on time extension ? t x i zcd 500 700 900 paxs ICB2FL03G controller for fluorescent lamp ballasts electrical characteristics final data sheet 47 v1.1, 2013-08-14 5.3.2.3 pfc bus voltage sense (pfcvs) 5.3.2.4 pfc pwm generation parameter symbol limit values unit test conditions min. typ. max. trimmed reference voltage v pfcvsref 2.47 2.50 2.53 v 1.2 % overvoltage turn off (109%) v pfcvsrup 2.68 2.73 2.78 v overvoltage turn on (105%) v pfcvslow 2.57 2.63 2.68 v overvoltage hysteresis v pfcvshys 70 100 130 mv 4 % rated bus voltage under voltage (75%) v pfcvsuv 1.835 1.88 1.915 v under voltage (12.5%) v pfcvsuv 0.237 0.31 0.387 v rated bus voltage (95%) v pfcvs95 2.325 2.38 2.425 v pfcvs bias current i pfcvsbias ?1.0 ? 1.0 av pfcvs = 2.5v parameter symbol limit values unit test conditions min. typ. max. initial on ? time 1) 1) when missing zero crossing signal t pfcon_initial ?4.0? sv pfczcd = 0v max. on ? time 2) 2) at the maxima of th e ac line input voltage t pfcon_max 18.0 24.0 28.0 s 0.45v < vpfcvs < 2.45v switch threshold from critcm into dcm t pfcon_min 160 270 370 ns repetition time 1) t pfcrep 47 52 57 sv pfczcd = 0v off time t pfcoff 42 47 52 s ICB2FL03G controller for fluorescent lamp ballasts electrical characteristics final data sheet 48 v1.1, 2013-08-14 5.3.2.5 pfc gate drive (pfcgd) parameter symbol limit values unit test conditions min. typ. max. pfcgd low voltage v pfcgdlow 0.4 0.7 0.9 v i pfcgd = 5ma 0.40.751.1 v i pfcgd = 20ma ?0.2 0.3 0.6 v i pfcgd = -20ma pfcgd high voltage v pfcgdhigh 10.0 11.0 11.6 v i pfcgd = -20ma 9.0 ? ? v i pfcgd = -1ma / v vcc 1) 1) v vcc = v vccoff + 0.3 v 8.5 ? ? v i pfcgd = -5ma / v vcc 1) pfcgd active shut down v pfcgasd 0.40.751.1 v i pfcgd = 20ma v vcc =5v pfcgd uvlo shut down v pfcgduvlo 0.3 1.0 1.5 v i pfcgd = 5ma v vcc =2v pfcgd peak source current i pfcgdsouce ? ?100 ? ma 2) + 3) 2) r load = 4 ? and c load = 3.3 nf 3) the parameter is not subject to a production test ? verified by design / characterization pfcgd peak sink current i pfcgdsink ?500? ma 2) + 3) pfcgd voltage during sink current v pfcgdhigh 11.0 11.7 12.3 v i pfcgdsinkh = 3ma pfc rise time t pfcgdrise 100 245 405 ns 2v > v lsgd > 8v 2) pfc fall time t pfcgdfall 20 45 70 ns 8v > v lsgd > 2v 2) ICB2FL03G controller for fluorescent lamp ballasts electrical characteristics final data sheet 49 v1.1, 2013-08-14 5.3.3 inverter section 5.3.3.1 low side current sense (lscs) parameter symbol limit values unit test conditions min. typ. max. overcurrent shut down volt. v lscsovc1 1.5 1.6 1.7 v 1) 1) overcurrent voltage threshold active during: st art up, soft start, ignition and pre-run mode overcurrent shut down volt. v lscsovc2 0.75 0.8 0.85 v 2) 2) overcurrent voltage threshold acti ve during: preheating and run mode duration of overcurrent t lscsovc 450 600 700 ns capacitive mode det. level 1 v lscscap1 30 50 73 mv during run mode capacitive mode duration 1 t lscscap1 ?280? ns 3) 3) during 2nd 50% duty cycle of lsgd in run mode capacitive mode det. level 2 v lscscap2 1.8 2.0 2.2 v during run mode capacitive mode duration 2 t lscscap2 ?50? ns 4) 4) active during turn on of the hsgd in run mode capacitive mode det. level 3 v lscscap3 ?70 -50 -27 mv capacitive mode duration 3 t lscscap3 ?280? ns 5) 5) active before turn on of the hsgd in run mode lscs bias current i lscsbias ?1.0 ? 1.0 a@ v lscs = 1.5v ICB2FL03G controller for fluorescent lamp ballasts electrical characteristics final data sheet 50 v1.1, 2013-08-14 5.3.3.2 low side gate drive (lsgd) 5.3.3.3 inverter c ontrol run (rfrun) parameter symbol limit values unit test conditions min. typ. max. lsgd low voltage v lsgdlow 0.4 0.7 1.0 v i lsgd = 5ma 1) 1) sink current 0.4 0.8 1.2 v i lsgd = 20ma 1) ?0.3 0.2 0.5 v i lsgd = - 20ma (source) lsgd high voltage v lsgdhigh 10.0 10.8 11.6 v 2) 2) i lsgd = - 20ma source current 9.0 ? ? v 3) 3) v ccoff + 0.3v and ilsgd = - 1ma source current 8.5 ? ? v 4) 4) v ccoff + 0.3v and ilsgd = - 5ma source current lsgd active shut down v lsgdasd 0.40.751.1 v v cc =5v / i lsgd = 20ma 1) lsgd uvlo shut down v lsgduvlo 0.3 1.0 1.5 v v cc =2v / i lsgd = 5ma 1) lsgd peak source current i lsgdsource ??50? ma 5) + 6) 5) load: r load = 10 ? and c load = 1nf 6) the parameter is not subject to a production test ? verified by design / characterization lsgd peak sink current i lsgdsink ?300? ma 5) + 6) lsgd voltage during 1) v lsgdhigh ? 11.7 ? v i lsgdsinkh = 3ma lsgd rise time t lsgdrise 100 245 405 ns 2v < v lsgd < 8v 5) lsgd fall time t lsgdfall 20 35 60 ns 8v > v lsgd > 2v 5) parameter symbol limit values unit test conditions min. typ. max. fixed start ? up frequency f startup 121.5 135 148.5 khz duration of soft start t softstart 91113.5ms 1) 1) shift start up frequency to preheating frequency rfrun voltage in run mode v rfrun ? 2.5 ? v @ 100 a ICB2FL03G controller for fluorescent lamp ballasts electrical characteristics final data sheet 51 v1.1, 2013-08-14 5.3.3.4 inverter control preheating (rfph, rtph) 5.3.3.5 restart after lamp removal (res) parameter symbol limit values unit test conditions min. typ. max. rfph voltage preheating v rfph ?2.5? vv rfph = 0v in run mode preheating frequency f rfph1 97 100 103 khz r rfph = r rfrun = 10k ? rfph max. current range i rfphmax ? ?1000 ? 550 a@ v rfph = 0v current for set preh. time i rtph ? ?100 ? a preheating time t rtph1 950 1000 1050 ms r rtph1 = 10k ? t rtph2 50 100 150 ms r rtph2 = 1k ? t rtph3 ?500? msr rtph3 = 5k ? t rtph4 ? 2000 ? ms r rtph4 = 20k ? t rtph5 ? 2500 ? ms r rtph5 = 25k ? parameter symbol limit values unit test conditions min. typ. max. high side filament in det. v res1 1.55 1.60 1.65 v u vlo , v cc < v ccon v res2 1.25 1.30 1.35 v v res3 ? 3.2 ? v run mode res current source i res1 ?53.2 ?42.6 ?32.0 av res = 1v ;lvs = 5 a i res2 ?44.2 ?35.4 ?26.6 av res = 2v ;lvs = 5 a i res3 ?26.6 ?21.3 ? 16.0 av res = 1v ;lvs = 30 a i res4 ?22.1 ?17.7 ?13.3 av res = 2v ;lvs = 30 a ICB2FL03G controller for fluorescent lamp ballasts electrical characteristics final data sheet 52 v1.1, 2013-08-14 5.3.3.6 lamp voltage sense (lvs) 5.3.3.7 high side gate drive (hsgd) parameter symbol limit values unit test conditions min. typ. max. source current before startup i lvssource ?5.0 ?3.0 ?2.0 av lvs = 0v enable lamp monitoring v lvsenable1 350 530 750 mv 1) 1) if v lvs < v lvsenable1 monitoring is disabled sink current for lamp det. i lvssink 8.0 12.0 18.0 av lvs > v lvsclamp positive clamping voltage v lvsclamp ?6.5? v@ i lvs = 300 a ac eolcurrent threshold i lvssourceac 190 210 230 app i lvs > i lvseolpp eol 1 positive eol current thr. i lvsdcpos 34 42 50 ai lvs > i lvsdcpos eol 2 negative eol current thr. i lvsdcneg ?50 ?42 ?34 ai lvs > i lvsdcneg eol 2 parameter symbol limit values unit test conditions min. typ. max. hsgd low voltage v hsgdlow 0.02 0.05 0.1 v i hsgd = 5ma (sink) 0.5 1.1 2.5 v i hsgd = 100ma (sink) ?0.4 ?0.2 ?0.05 v i lsgd = - 20ma (source) hsgd high voltage v hsgdhigh 9.7 10.5 11.2 v v cchs =15v i hsgd = - 20ma (source) 7.8 ? ? v v cchsoff + 0.3v i hsgd = - 1ma (source) hsgd active shut down v hsgdasd 0.05 0.22 0.5 v v cchs =5v i hsgd = 20ma (sink) hsgd peak source current i hsgdsource ??50? mar load = 10 ? +c load = 1nf 1) 1) the parameter is not subject to a production test ? verified by design / characterization hsgd peak sink current i hsgdsink ?300? mar load = 10 ? +c load = 1nf 1) hsgd rise time t hsgdrise 120 220 300 ns 2v < v lsgd < 8v r load = 10 ? +c load = 1nf hsgd fall time t hsgdfall 20 35 70 ns 8v > v lsgd > 2v r load = 10 ? +c load = 1nf ICB2FL03G controller for fluorescent lamp ballasts electrical characteristics final data sheet 53 v1.1, 2013-08-14 5.3.3.8 timer section 5.3.3.9 built-in customer test mode delay timer 1 t timer1 70 100 160 ms for lamp detection delay timer 2 t timer2 74 84 94 ms for v bus > 95% inverter time t inv 100 130 160 s inverter dead time max t deadmax 1.75 2.1 2.40 s inverter dead time min t deadmin 0.81.051.3 s ? inverter dead time max t deadmax ?200 ? 200 ns ? inverter dead time min t deadmin ?200 ? 200 ns min. duration of ignition t ignition 34 40 48 ms max. duration of ignition t noignition 197 ? 236 ms duration of pre ? run t prerun 565 625 685 ms voltage at rtph pin v rtph 0 v preheating time = 0 ms (skipped preheating) voltage at rtph pin v rtph 5.0 v 1) 1) tolerance for this voltage is 5% ic remains in preheating voltage at lvs v lvs 0 v disables lamp voltage sense voltage at res pin v res 0 v disable the filament detection voltage at rfph pin v rfph 5.0 v 1) built-in customer test mode - clock acceleration. decreasing time for the following procedures: preheating by factor 4 timeout ignition by factor 2 pre-run by factor 15; eol by 60 voltage at rfrun pin v rfrun 5.0 v 1) voltage at vcc pin v cc > 14.0 v voltage at res pin v res 0v ICB2FL03G controller for fluorescent lamp ballasts electrical characteristics final data sheet 54 v1.1, 2013-08-14 5.3.4 parameter limits for extended temperature range down to -40c for any other parameter which is not listed belo w, the -25c limit is also valid for -40c parameter symbol limit values unit test conditions min. typ. max. junction temperature t j -40 150 c lsvcc turn-on threshold v vccon 13.48 14.0 14.5 v hysteresis vcc zener clamp voltage i vcczener 2.5 - 5.05 ma v vcc = 17.5v/v res = 5v hsvcc quiescent current i hsvccqu2 0.26 0.65 1.2 ma v hsvcc > v hsvccon hsvcc turn-on threshold hsvcc turn-off threshold hsvcc turn-on/off hyst. v hsvccon v hsvccoff v hsvcchy 9.8 8.08 1.4 10.4 8.6 1.7 11.0 9.3 2.03 v v v hysteresis over current blanking + propagation delay t pfccsoff 140 200 262 ns leading edge blanking t blanking 180 250 315 ns pulse width when v pfccs > 1.0 v clamping of pos. voltages v pfczcdpclp 4.1 4.6 5.12 v i pfczcdsink = 2ma clamping of neg. voltages v pfczcdnclp -1.69 -1.4 -1.0 v i pfczcdsource = -2ma pfczcd ringing suppress. time t ringsup 350 500 660 ns limit value for on time extension ? t x i zcd 498 700 900 paxs trimmed reference voltage v pfcvsref 2.468 2.50 2.53 v 1.2 % overvoltage turn off (109%) v pfcvsrup 2.677 2.73 2.78 v overvoltage turn on (105%) v pfcvslow 2.567 2.63 2.68 v under voltage (75%) v pfcvsuv 1.832 1.88 1.915 v rated bus voltage (95%) v pfcvs95 2.320 2.38 2.425 v max. on ? time t pfcon_max 18.0 24.0 28.6 s 0.45v < vpfcvs < 2.45v off time t pfcoff 42 47 52.5 s pfcgd low voltage v pfcgdlow 0.4 0.7 0.92 v i pfcgd = 5ma 0.4 0.75 1.12 v i pfcgd = 20ma -0.2 0.3 0.62 v i pfcgd = -20ma pfcgd high voltage v pfcgdhigh 10.0 11.0 11.6 v i pfcgd = -20ma 8.98 ? ? v i pfcgd = -1ma / v vcc 1) 8.47 ? ? v i pfcgd = -5ma / v vcc 1) pfcgd active shut down v pfcgasd 0.4 0.75 1.12 v i pfcgd = 20ma v vcc =5v pfcgd uvlo shut down v pfcgduvlo 0.3 1.0 1.56 v i pfcgd = 5ma v vcc =2v pfc rise time t pfcgdrise 100 245 450 ns 2v > v lsgd > 8v 2) pfc fall time t pfcgdfall 20 45 72 ns 8v > v lsgd > 2v 2) lsgd low voltage v lsgdlow 0.4 0.7 1.02 v i lsgd = 5ma (sink) 0.4 0.8 1.22 v i lsgd = 20ma (sink) -0.3 0.2 0.53 v i lsgd = -20ma (source) ICB2FL03G controller for fluorescent lamp ballasts electrical characteristics final data sheet 55 v1.1, 2013-08-14 lsgd high voltage v lsgdhigh 10.0 10.8 11.6 v 8.98 ? ? v 8.47 ? ? v lsgd active shut down v lsgdasd 0.4 0.75 1.12 v v cc =5v / i lsgd = 20ma (sink) lsgd uvlo shut down v lsgduvlo 0.3 1.0 1.6 v v cc =2v / i lsgd = 5ma (sink) lsgd rise time t lsgdrise 100 245 460 ns 2v < v lsgd < 8v 3) lsgd fall time t lsgdfall 20 35 61 ns 8v > v lsgd > 2v fixed start ? up frequency f startup 120 135 148.5 khz duration of soft start t softstart 9 11 13.56 ms 4) run frequency f rfrun 49 50 51.07 khz r rfrun = 10k ? rfrun max. current range i rfrunmax ? -1000 -612 a@ v rfrun = 0v rfph max. current range i rfphmax ? -1000 -512 a@ v rfph = 0v preheating time t rtph1 920 1000 1050 ms r rtph1 = 10k ? high side filament in det. v res1 1.546 1.60 1.65 v u vlo , v cc < v ccon v res2 1.247 1.30 1.35 v res current source i res1 -53.2 -42.6 -30.5 av res = 1v ;lvs = 5 a i res2 -44.2 -35.4 -25.1 av res = 2v ;lvs = 5 a i res3 -26.6 -21.3 -15 av res = 1v ;lvs = 30 a i res4 -22.1 -17.7 -12.3 av res = 2v ;lvs = 30 a source current before startup i lvssource -5.0 -3.0 -1.9 av lvs = 0v sink current for lamp det. i lvssink 7.0 12.0 18.0 av lvs > v lvsclamp ac eolcurrent threshold i lvssourceac 186 210 230 app i lvs > i lvseolpp eol 1 hsgd low voltage v hsgdlow 0.018 0.05 0.1 v i hsgd = 5ma (sink) 0.46 1.1 2.5 v i hsgd = 100ma (sink) -0.4 -0.2 -0.04 v i lsgd = - 20ma (source) hsgd active shut down v hsgdasd 0.041 0.22 0.5 v v cchs =5v i hsgd = 20ma (sink) hsgd fall time t hsgdfall 19 35 70 ns 8v > v lsgd > 2v r load = 10 ? +c load = 1nf delay timer 1 t timer1 70 100 163.6 ms for lamp detection inverter time t inv 100 130 163 s inverter dead time max t deadmax 1.75 2.1 2.50 s inverter dead time min t deadmin 0.8 1.05 1.33 s ? inverter dead time max t deadmax -240 ? 200 ns ? inverter dead time min t deadmin -230 ? 200 ns 1) v vcc = v vccoff + 0.3 v 2) r load = 4 ? and c load = 3.3nf 3) load: r load = 10 ? and c load = 1nf 4) shift start up frequency to preheating frequency parameter symbol limit values unit test conditions min. typ. max. ICB2FL03G controller for fluorescent lamp ballasts application example final data sheet 56 v1.1, 2013-08-14 6 application example 6.1 schematic ballast 54w t5 single lamp figure 37 application circuit of ballast for si ngle fluorescent lamp voltage mode preheating ICB2FL03G controller for fluorescent lamp ballasts application example final data sheet 57 v1.1, 2013-08-14 6.2 bill of material figure 38 bill of material ICB2FL03G controller for fluorescent lamp ballasts application example final data sheet 58 v1.1, 2013-08-14 6.3 multi lamp ballast topologies (series connection) figure 39 application circuit of ballast for tw o fluorescent lamps voltage mode preheating rfrun rfph rtph vcc pfczcd pfcgd pfcvs pfccs hsgd hsvcc hsgnd lsgd lscs lvs gnd 90 ... 270 vac ICB2FL03G res ICB2FL03G controller for fluorescent lamp ballasts package outline final data sheet 59 v1.1, 2013-08-14 7 package outline 7.1 outline dimensions of pg-dso-16 figure 40 package outline with creepage distance published by infineon technologies ag www.infineon.com |
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